Complimentary-Metal-Oxide-Semiconductor (CMOS) circuits designs based on the advanced Silicon-On-Insulator (SOT) technology are continuously proving to be better match to Gallium-Arsenide (GaAs) for the compact Radio-Frequency (RF) building-blocks. CMOS can be very densely integrated into Chips that it is the only known technology today that can monolithically integrate the RF modules and Power-Amplifiers (PAs) with the digital basebands. Such integration of RF transceivers and baseband processors in one compact chip is already gaining wide momentum as its demand in the industry is continuing to increase with the continuous growth of the High-Speed Downlink Packet Access (HSDPA)-enabled networks, and the continuous requirements for higher data throughput. This is simply due to the continuous on-going scale-up of the multimedia Cellular applications and that are only projected to further increase with the recent surge of the Internet-Of-Things (IOT). Yet much of the reason that is still impeding the implementations of the conventional CMOS into the mainstream PAs and other RF modules is their relatively lower currents and reduced bandwidths as compared to GaAs devices. These devices profit from a higher carrier Mobility that is boosting their currents and their bandwidths. The Fully-Depleted Silicon-On-Insulator (FD-SOI) MOS offers an excellent suppression of the junction capacitances, and has an inherently lower Threshold-Voltage (VT) as compared to the conventional MOS on bulk substrates. This gives it the good leverage it needs against the less matured GaAs technology in current and in bandwidth. CMOS based on SOI can realize speed and bandwidth based on this suppression of the junction capacitances with a Buried-Oxide film (BOX). Additionally, this same suppression of the junction capacitances suppresses the junction leakage and results in reduced overall parasitic power consumption.
One major obstacle and that is the Floating-Body-Effect (FBE) is still issue that is preventing this SOI MOS from scaling to larger peripheries to meet requirements for the high currents that the analog RF Cellular PAs require. These requirements were well described by Ted Johansson, Senior Member, IEEE, and Jonas Fritzin, Member, IEEE, “A Review of Watt-level CMOS RF power amplifiers”, IEEE Transactions on Microwave Theory and Techniques, vol. 62, iss. 1, pp. 111-124, December 2013. This obstacle arises simply because both, higher Drain biasing (VD) and higher current (IDevice) increase the undesired Impact-Ionizations current (II-current) that governs the FBE, and structures with large peripheries do naturally deliver higher currents in proportion to the size of their “effective” Gate-Widths (WGeff). Accurate model for Impact-Ionizations current was described by X. Gu, G. Gildenblat, G. Workman, S. Veeraraghavan, S. Shapira and K. Stiles, “A Surface-Potential-Based Extrinsic Compact MOSFET Model”, Technical Proceedings of the 2003 Nanotechnology Conference and Trade Show, vol. 2, pp. 364-367, San Francisco, February 2003.
The physical mechanism that governs the FBE was well detailed by Vandana B., “Study of Floating Body Effect in SOI Technology”, International Journal of Modern Engineering Research, vol. 3, iss. 3, pp. 1817-1824. June 2013. FBE is mostly inherent to the SOI N-type MOS (NMOS) device and it manifests itself in Partially-Depleted Silicon-On-Insulator (PD-SOI) NMOS with build-up of positively charged Holes in P_Body that are generated from Impact-Ionizations at the Drain's edge of the device and which, for fixed Gate bias, continue to accumulate with increasing Drain Supply-voltage till they sufficiently lower the barrier under the channel between P_Body and Source and start to abruptly diffuse to Source causing an up-tick of the IDevice. This latches-up the built-in parasitic Bipolar structure from which the device will no longer turn-off, even after the Gate voltage is brought back to values lower than VT. This up-tick of current (or the “kink-effect”, as is often referred to in technical literatures) is totally undesirable as it causes a distorted linearity of the RE PAs, a degraded overall device performance, a reduced signal-to-noise ratio, and can result in false outputs from Logic Gates. While this kink-effect is generally absent in the more advanced FD-SOI NMOS, because this device operates with its Body/Source barrier already lowered due to the inherent full-depletion of its Body, it still does exhibit the Bipolar latch-up and is more susceptible to it since it takes less Impact-Ionizations current to more strongly forward-bias an already lowered barrier. This FBE mechanism is therefore the source to the obstacle that is preventing the scaling of SOI CMOS to larger peripheries. This is due to the resulting inherent higher Impact-Ionizations of these structures from their inherent higher IDevice.
The use of multi-legs (or multi-fingers) design that decomposes a large-periphery structure into dozens, hundreds or potentially thousands of paralleled transistors of smaller Gate-Widths may deliver the desired high IDevice while still suppressing the FBE due to a lower current per leg (or per finger). Such large-periphery multi-legs design is however well known to substantially increase the parasitic capacitances and reduce the device bandwidth. Its effect on increasing parasitic capacitances and reducing bandwidth in conventional MOS was well evidenced and reported by Kwangseok Han, Jeong-hu Han, Minkyu Je and Hyungcheol Shin, “RF Characteristics of 0.18-μm CMOS Transistors”, Journal of the Korean Physical Society, vol. 40, no. 1, pp. 45-48, January 2002. The device bandwidth was shown in this work to dramatically collapse in proportion to the increase of the total number of its paralleled legs. Its ft collapsed from 80 GHz to 55 GHz with the increase of the number of its paralleled legs for same WGeff from 20 legs to 160 legs. This is attributed to the increases of the parasitic Gate-to-Body, Gate-to-Source, and Gate-to-Drain capacitances with this increase of the total number of paralleled legs. Multi-legs large peripheries MOS designs based on the SOI can be no exception to a similar trend, simply because of a similar increase of their parasitic capacitances. Furthermore, it was specifically shown that the use of multi-legs designs based on FINFETs does further amplify this reduction of the device bandwidth. That is simply because of the three-dimensional nature of the FINFET that tends to inherently increase its parasitic capacitances. Comparative assessments between planar SOI MOS and FINFETs clearly demonstrated this effect on the device performance. These assessments were carried by Jean-Pierre Raskin, “SOI Technology: An Opportunity for RF Designers?”, Journal of telecommunications and Information technology, no. 4, pp. 3-17, April 2009; and by J. Borrernans, B. Parvais, and M. Dehan, “Perspective of RF Design in Future Planar and FINFET CMOS”, Radio frequency Integrated Circuits Symposium, pp. 75-78, Atlanta Ga., 2008. Therefore, while it is indisputable today that the FINFET device does possess the excellent potential enabling it to comply with the downscaling requirements of the ITRS for logic operations (Ion/Ioff) its potential in the analog RF appears less promising.
Higher current devices are also as important for low insertion-loss RF-switches, and for an enhanced overall performance on all the analog and digital Integrated-Circuits (ICs).
Based on the above, a best approach to achieve the desired high IDevice and high bandwidth for the analog RF PAs based on SOI CMOS would be through the incorporation of planar designs that are totally free of FBE and utilize largest possible Gate-width per leg so to maximize the bandwidth. This may totally eliminate the need for multi-legs designs, or when extreme high currents are still essentials, it can still minimize the total number of legs required to meet the target device current while still boosting the bandwidth. The larger is the Gate-width per leg, the less paralleled legs will be required to meet the target IDevice, and consequently, the higher becomes the operational bandwidth. Still, due to their high current per leg (or per finger), large peripheries SOI MOS structures that incorporate a large Gate-width per leg do still suffer from FBE and Bipolar current latch-up. Particularly most susceptive to this notorious FBE are the ICs that depend on relatively high Supply-voltages (>3.3V) for their normal operating modes. These tend to typically encompass longer Gate-Lengths to accommodate such high voltages to their Drains. Some of those ICs are in Cellular handheld devices and other portable electronics. Again, this is simply because of the fact that not only the WGeff in SOI-based CMOS dictates the amount of II-current that governs the FBE, but also the magnitude of its Supply-voltage (VD) and that of its Front-Gate bias (VGS). Such ICs include the Cellular RF PAs and some other analog modules such as the RF-switches, regulators and power-management ICs.
The most effective technique that is in use today to circumvent this kink-effect and the Bipolar current latch-up in single-legged SOT MOS, is through the incorporation of a Body-Tied-Source (BTS) within the Device layout. This BTS consists of no more than highly doped region(s) within the device layout structure, that is/are doped counter to the doping of the Source and Drain, and that is/are wired to the Source with Nickel- or Cobalt Silicide. This BTS allows the bulk of the II-current in the device Body to sink-out to it. It reduces therefore the amount of Holes in an NMOS that can diffuse from Body to Source and latch-up the parasitic Bipolar structure. The pitfall of this technique however is that it reduces the WGeff of the device, and correspondingly, its IDevice for given full peripheral width (WG) of device structure. The capability of a BTS to reduce this Bipolar current gain in FD-SOI MOS was demonstrated by K. Hirose, H. Saito, S. Fukuda, Y. Kuroda, S. Ishii, D. Takahashi, and K. Yamamoto, “Analysis of Body-Tie Effects on SEU Resistance of Advanced FD-SOI SRAMs Through Mixed-Mode 3-D Simulations”, IEEE transactions on Nuclear Science, vol. 51; mo. 6, pp. 3349-3353, December 2004. FIG. 1 illustrates this fact in showing side by side two comparative layout schematics of SOI-based NMOS structures: One optimized layout (right-hand side) that is capable of suppressing FBE for given bias with minimum area consumed by BTS. And, another un-optimized layout (left-hand side), of same full peripheral width (WG), that used extra BTS area that is not actually needed to suppress the FBE for same bias. The optimized layout gives higher WGeff, and does correspondingly give superior device performance manifested with higher current for same bias and same peripheral footprint; it is more area-efficient.
As more large peripheries devices get integrated monolithically to form functional ICs, summative or total combined parasitic area from BTS alone can become substantially large. Consequently, a tremendously large die-size can result unless area consumed by BTS within each single MOS device gets minimized relative to the device targeted performance (optimizing the performance for area-efficiency). The other alternative would be to rely on devices built with hundreds or potentially thousands of multi-legs structures of narrower Gate-widths (≦0.5 μm) having no BTS; however and as was already stated, this causes severe hit on the bandwidth.
If for instance through effective optimization, a1 μm2 of BTS area in an SOI NMOS gets reduced by 40%, the device will benefit from gaining 40% increase in its drive current for same WG. Conversely, this WG can be reduced by 40% for a same drive current. In an IC containing 2000 SOI NMOS, a corresponding 800 μm2 reduction in its total peripheral layout would then result for same or better performance. These are serious improvements in area-efficiency and in performance that cannot be overlooked.
Similar to SOI, Silicon-On-Sapphire (SOS) utilizes Sapphire (Al2O3) as the buried film instead of BOX to suppress the junction capacitances. The Silicon-On-Nothing (SON) process on the other hand allows the buried dielectric, which may still be a dielectric but can also be an air gap, to locate only underneath the Gate and the spacers regions of the device. It still maintains the desired coupling between the Front-Gate and the Back-Gate (a “must” criterion in FD-SOI MOS). The “claimed” advantage of this SON structure over SOI and SOS is in its reduced series resistance, and in its lessened self-heating due to less volume consumed by BOX or sapphire. Both of these two technologies, the SOS and the SON, are equally susceptible to the FBE, and do both possess the exact same obstacle as SOI to the scalabilities of their devices to larger peripheries.